Aaeon GENE-TC05 Instrukcja Użytkownika

SubCompact Board G E N E - T C 0 5 GENE-TC05 Intel® Atom™ E680/ E620/ E620T (E620T for WiTAS2) Processor Intel® EG20T

SubCompact Board GENE-TC05 1.2 Features  Intel® Atom™ E680/E620/E620T Processor (E620T is for WiTAS2)  Intel® EG20T PCH  Onboard DDR2 667/800 M

SubCompact Board GENE-TC05 Appendix B I/O Information B - 5 B.3 IRQ Mapping Chart

SubCompact Board GENE-TC05 Appendix B I/O Information B - 6 B.4 DMA Channel Assignments

SubCompact Board GENE-TC05 Appendix C Mating Connector C - 1 Mating Connecotor Appendix C

SubCompact Board GENE-TC05 Appendix C Mating Connector C - 2 C.1 List of Mating Connectors and Cables The table notes mating connectors and availabl

SubCompact Board GENE-TC05 Appendix C Mating Connector C - 3 CN15 Keyboard / Mouse Connector Catch A003-290 KB/MS Cable 1700060152 CN17 USB

SubCompact Board GENE-TC05 Appendix D AHCI Setting D-1 AHCI Setting A ppendixD

SubCompact Board GENE-TC05 Appendix D AHCI Setting D-2 D.1 WIN XP OS installation Note: BIOS Setting Requirement : “BIOS SettingAdvanced Launch

SubCompact Board GENE-TC05 Appendix D AHCI Setting D-3 Step 3: Setup OS Step 4: Press “F6”

SubCompact Board GENE-TC05 Appendix D AHCI Setting D-4 Step 5: Choose “S” Step 6: Choose “Intel(R) PCH EG20T SATA AHCI Controller For Windows XP”

SubCompact Board GENE-TC05 Appendix D AHCI Setting D-5 Step 7: It will show the model number you select and t

SubCompact Board GENE-TC05 1.3 Specifications System  Form Factor 3.5”  Processor Intel® Atom™ E680 1.6GHz/ E620 600MHz/ E620T 600MHz (E620T is

SubCompact Board GENE-TC05 Chapter 1 General Information 1 - 5 Storage Temperature -40°F ~ 176°F (-40°C ~ 80°C)  Operating Humidity 0% ~ 90% r

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-1 Quick In

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-2 2.1 Safety Precautions Always completely disconnect the power cord fr

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-3 2.2 Location of

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-4 Solder Side

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-5 2.3 Mechanical

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-6 Solder Side

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-7 2.4 List of Jum

SubCompact Board G E N E - T C 0 5 i Copyright Notice This document is copyrighted, 2014. All rights are reserved. The original manufactu

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-8 CN11 COM Port #4 CN12 COM Port #5 CN13 COM Port #6 CN14 USB Port #4 CN

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-9 to the CPU boar

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-10 2.7 LVDS Operating Voltage Selection (JP1) JP1 Function 1-2 +5V 2-3 +3.

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-11 2.12 RS-232/42

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-12 5 +3.3V 6 LFRAME# 7 LRESET# 8 Ground 9 LPC_CLK 10 LDRQ#0 11 LDRQ#1 12 S

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-13 Output Input P

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-14 9 Ground RS-485 Pin Signal Pin Signal 1 TXD- 2 N/C 3 N/C 4 N/C 5 TXD+

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-15 2.22 +5VSB Out

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-16 2.24 COM Port #4 (CN11) Pin Signal Pin Signal 1 DCDD 2 DSRD 3 RXD 4 R

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-17 3 Data4+ 4 Gro

SubCompact Board G E N E - T C 0 5 ii Acknowledgments All other products’ name or trademarks are properties of their respective owners. 

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-18 5 Ground 2.31 Power Input (Vin) (CN18) Pin Signal 1 +12V 2 Ground 2.3

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-19 2.34 SATA Conn

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-20 2 Data1- 6 Data2- 3 Data1+ 7 Data2+ 4 Ground 8 Ground 2.38 Audio Line I

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-21 13 N/C 14 +5V

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-22 2.41 SIM Card Socket (CN28) Pin Signal Pin Signal 1 UIM_PWR 2 UIM_RST 3

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-23 P13 +3.3V P14

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-24 41 +3.3V Standby 42 N/C 43 Ground 44 N/C 45 N/C 46 N/C 47 N/C 48 +1.5V

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-25 39 +3.3V Stand

SubCompact Board G E N E - T C 0 5 Chapter 2 Quick Installation Guide 2-26 Below Table for China RoHS Requirements 產品中有毒有害物質或元素名稱及含量 AAEON Main Bo

SubCompact Board GENE-TC05 Chapter 3 AMI BIOS Setup 3-1 AMI Chapter 3BIOS Setup

SubCompact Board G E N E - T C 0 5 iii Packing List Before you begin installing your card, please make sure that the following materials

SubCompact Board GENE-TC05 3.1 System Test and Initialization These routines test and initialize board hardware. If the routines encounter an error

SubCompact Board GENE-TC05 3.2 AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration.

SubCompact Board GENE-TC05 Setup Menu Press ‘Delete’ Key to enter Setup menu Main Chapter 3 AMI BIOS Setup 3-4

SubCompact Board GENE-TC05 Advanced Chapter 3 AMI BIOS Setup 3-5

SubCompact Board GENE-TC05 ACPI Settings Options summary: Disable Enable Hibernation Enable Optimal Default, Failsafe DefaultEnables or Disables S

SubCompact Board GENE-TC05 Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed. CPU Configuration Options

SubCompact Board GENE-TC05 Enabled Optimal Default, Failsafe Default Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology)

SubCompact Board GENE-TC05 Disabled Optimal Default, Failsafe Default Enhanced C1 Enabled Enable or Disable Enhanced C1 State Disable Enhanced C2

SubCompact Board GENE-TC05 Digital IO Options summary: Input Optimal Default, Failsafe Default GPI0-3 Device Output Set GPI0 as Input or Output In

SubCompact Board GENE-TC05 AHCI SATA Configuration Options summary: Disabled PORT 0 Enable Optimal Default, Failsafe Default Enable/Disable PORT 0

SubCompact Board G E N E - T C 0 5 iv Contents Chapter 1 General Information 1.1 Introduction ...

SubCompact Board GENE-TC05 Wake On Lan Configuration Options summary: Disabled Wake On Lan Enable Optimal Default, Failsafe Default Enable/Disable

SubCompact Board GENE-TC05 USB Configuration Options summary: Enabled Optimal Default, Failsafe Default Disabled Legacy USB Support Auto Enable

SubCompact Board GENE-TC05 10 sec 20 sec Optimal Default, Failsafe Default The time-out value for Control, Bulk, and Interrupt transfers 1 sec

SubCompact Board GENE-TC05 Second Super IO Configuration Chapter 3 AMI BIOS Setup 3-15

SubCompact Board GENE-TC05 Serial Port 3 Configuration Chapter 3 AMI BIOS Setup 3-16

SubCompact Board GENE-TC05 Serial Port 4 Configuration Chapter 3 AMI BIOS Setup 3-17

SubCompact Board GENE-TC05 Serial Port 5 Configuration Chapter 3 AMI BIOS Setup 3-18

SubCompact Board GENE-TC05 Serial Port 6 Configuration Options summary: Disabled Serial Port Enabled Optimal Default, Failsafe Default Enable or D

SubCompact Board GENE-TC05 IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12; IO=2F0h; IRQ=3,4,5,6,7,9,10,11,12; IO=2E0h; IRQ=3,4,5,6,7,9,10,11,12; IO=2E8h; IRQ=

SubCompact Board GENE-TC05 IO=2E0h; IRQ=3,4,5,6,7,9,10,11,12; IO=2E0h; IRQ=5; Optimal Default, Failsafe Default IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12;

SubCompact Board G E N E - T C 0 5 v 2.18 COM Port #2 (CN5) ... 2-13 2.19 +5V Output For SAT

SubCompact Board GENE-TC05 Super IO Configuration Chapter 3 AMI BIOS Setup 3-22

SubCompact Board GENE-TC05 Serial Port 1 Configuration Chapter 3 AMI BIOS Setup 3-23

SubCompact Board GENE-TC05 Serial Port 2 Configuration Options summary: Disabled Serial Port Enabled Optimal Default, Failsafe Default Enable or

SubCompact Board GENE-TC05 IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12; IO=2F0h; IRQ=3,4,5,6,7,9,10,11,12; IO=2E0h; IRQ=3,4,5,6,7,9,10,11,12; IO=2F8h; IRQ=

SubCompact Board GENE-TC05 H/W Monitor Chapter 3 AMI BIOS Setup 3-26

SubCompact Board GENE-TC05 Chipset Chapter 3 AMI BIOS Setup 3-27

SubCompact Board GENE-TC05 North Bridge Chipset Configuration Options summary: Enabled, 1MB Enabled, 4MB Enabled, 8MB Optimal Default, Failsaf

SubCompact Board GENE-TC05 Select the amount of system memory used by the Integrated Graphics Device. Enabled, 512MB Enabled, 256MB Optimal Defau

SubCompact Board GENE-TC05 Boot Display Configuration Options summary: Auto Optimal Default, Failsafe Default IGD Primary Display PEG Select whic

SubCompact Board GENE-TC05 Select Boot Display Device Auto Optimal Default, Failsafe Default Forced Flat Panel Scaling Disabled Select Flat Panel

SubCompact Board G E N E - T C 0 5 vi 2.43 Mini Card Slot #1 (PCIE1) ... 2-23 2.44 Mini Card Slot #2 (

SubCompact Board GENE-TC05 Select DPST Control South Bridge Chipset Configuration Options summary: Auto Optimal Default, Failsafe Default IGD Pri

SubCompact Board GENE-TC05 PCI Express Ports Configuration Chapter 3 AMI BIOS Setup 3-33

SubCompact Board GENE-TC05 PCI Express Root Port 0 Chapter 3 AMI BIOS Setup 3-34

SubCompact Board GENE-TC05 PCI Express Root Port 1 Chapter 3 AMI BIOS Setup 3-35

SubCompact Board GENE-TC05 PCI Express Root Port 2 Chapter 3 AMI BIOS Setup 3-36

SubCompact Board GENE-TC05 PCI Express Root Port 3 Chapter 3 AMI BIOS Setup 3-37

SubCompact Board GENE-TC05 PCI-to-PCI Bridge Options summary: Disabled PCI Express Root Port 0Enabled Optimal Default, Failsafe Default PCI Expres

SubCompact Board GENE-TC05 Enabled Optimal Default, Failsafe Default PCI Express Root Port 2 Settings Disabled PCI Express Root Port 3Enabled Optim

SubCompact Board GENE-TC05 PPM Config Options summary: Disabled C-state POPUP Enabled Optimal Default, Failsafe Default Enable/Disable C-state POP

SubCompact Board GENE-TC05 Boot Options summary: Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enables or disables Quiet Boot opt

SubCompact Board GENE-TC05 Chapter 1 General Information 1- 1 General Chapter 1Information

SubCompact Board GENE-TC05 Setup Prompt Timeout Integer Number of seconds to wait for setup activation key. 65535(0xFFFF) means indefinite waiting.

SubCompact Board GENE-TC05 Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password,

SubCompact Board GENE-TC05 Chapter 3 AMI BIOS Setup 3-44

SubCompact Board GENE-TC05 Chapter 3 AMI BIOS Setup 3-45 Save & Exit

SubCompact Board GENE-TC05 Chapter 4 Driver Installation 4 -1 Driver Chapter 4Installation

SubCompact Board GENE-TC05 . The GENE-TC05 comes with a CD-ROM that contains all drivers your need. Follow the sequence below to install the driver

SubCompact Board GENE-TC05 4.1 Installation: Insert the GENE-TC05 DVD-ROM into the CD-ROM Drive. And install the drivers from Step 1 to Step 6 in

SubCompact Board GENE-TC05 Chapter 4 Driver Installation 4 -4 Step 4 – Install LAN Driver 1. Click on the Step 4 - Intel 82574L Ethernet folde

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-1 Programming the Appendix AWatchdog Timer

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-2 A.1 Programming GENE-TC05 utilizes W83627DHG-P chipset as its watchdog tim

SubCompact Board GENE-TC05 1.1 Introduction AAEON, a leading embedded boards manufacturer, is pleased to announce the debut of their new generation

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-3 (3) Exit the W83627DHG config Mode. Undesired r

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-4 = 010 Power LED pin is driven low. = 011 Power LED pin outputs 2H

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-5 WatchDog Timer Register II (Index=F6h, Default=0

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-6 = 1 Force Watchdog Timer time-out event: this bit is self-clearing

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-7 A.2 W83627DHG Watchdog Timer Initial Program Exa

SubCompact Board GENE-TC05 Appendix A Programming the Watchdog Timer A-8 ;/////////////////////////////////////////////////////////////////////////

SubCompact Board GENE-TC05 Appendix B I/O Information B - 1 I/O Information Appendix B

SubCompact Board GENE-TC05 Appendix B I/O Information B - 2 B.1 I/O Address Map

SubCompact Board GENE-TC05 Appendix B I/O Information B - 3

SubCompact Board GENE-TC05 Appendix B I/O Information B - 4 B.2 Memory Address Map